sim: riscv: invert sim_cpu storage
authorMike Frysinger <vapier@gentoo.org>
Tue, 1 Nov 2022 06:15:34 +0000 (12:00 +0545)
committerMike Frysinger <vapier@gentoo.org>
Wed, 21 Dec 2022 05:00:01 +0000 (00:00 -0500)
commit5409cab77ed607c4bb87160cf98861fad1e97381
treeda379b08e4fc0c341ab249a9a8604239bffa453b
parent3d165c11f0a91b9b32da30ac4ec42a3da2da6218
sim: riscv: invert sim_cpu storage
sim/riscv/interp.c
sim/riscv/sim-main.c
sim/riscv/sim-main.h