Add support for variable length Xilinx SRL > 128
authorEddie Hung <eddieh@ece.ubc.ca>
Wed, 20 Mar 2019 00:44:33 +0000 (17:44 -0700)
committerEddie Hung <eddieh@ece.ubc.ca>
Wed, 20 Mar 2019 00:44:33 +0000 (17:44 -0700)
commit5445cd4d00349f9d04f9e78c7c2804306fac6b65
treee95ed2958855afbf5ad375028cea5cfd54ec1006
parentae2a625d0507c9e7476497e0064ffa003aa761f1
Add support for variable length Xilinx SRL > 128
passes/techmap/shregmap.cc
techlibs/xilinx/cells_map.v