Allow defining input ports as "input logic" in SystemVerilog
authorRuben Undheim <ruben.undheim@gmail.com>
Mon, 20 Jun 2016 18:16:37 +0000 (20:16 +0200)
committerRuben Undheim <ruben.undheim@gmail.com>
Mon, 20 Jun 2016 18:16:37 +0000 (20:16 +0200)
commit545bcb37e8fa569d88374f92aafdcc1004e9b587
tree8df204605907e01759969afa2386274ea398c620
parent541083cf329addb57117618de41697dd010d07cf
Allow defining input ports as "input logic" in SystemVerilog
frontends/verilog/verilog_parser.y