Added module->remove(), module->addWire(), module->addCell(), cell->check()
authorClifford Wolf <clifford@clifford.at>
Mon, 21 Jul 2014 10:02:55 +0000 (12:02 +0200)
committerClifford Wolf <clifford@clifford.at>
Mon, 21 Jul 2014 10:02:55 +0000 (12:02 +0200)
commit54b0f2e659ac0c34c69b0c251c72b2a90fe8e6b6
tree14e1e4c9b7b9d015f4781405c1b77738ac5fcdf6
parentcaae6e19dffde4d76b30af3fd1f9751f4ec37fdc
Added module->remove(), module->addWire(), module->addCell(), cell->check()
kernel/rtlil.cc
kernel/rtlil.h