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(parent: 9e6f803) | patch
sim: Move the BaseTLB to src/arch/generic/
authorAndreas Sandberg <Andreas.Sandberg@ARM.com>
Wed, 11 Feb 2015 15:23:27 +0000 (10:23 -0500)
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>
Wed, 11 Feb 2015 15:23:27 +0000 (10:23 -0500)
commit550c31849024a2184887df87aae39617ebfe0d6a
tree53cc5e91d0961b0215c614141fdc380b30c76951tree
parent9e6f803254cbf3f5f491775debdc6593c3329da8commit | diff
sim: Move the BaseTLB to src/arch/generic/

The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.

--HG--
rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py
rename : src/sim/tlb.cc => src/arch/generic/tlb.cc
rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
19 files changed:
src/arch/alpha/tlb.hh diff | blob | history
src/arch/arm/stage2_lookup.hh diff | blob | history
src/arch/arm/tlb.hh diff | blob | history
src/arch/generic/BaseTLB.py [new file with mode: 0644] blob
src/arch/generic/SConscript diff | blob | history
src/arch/generic/tlb.cc [new file with mode: 0644] blob
src/arch/generic/tlb.hh [new file with mode: 0644] blob
src/arch/mips/tlb.hh diff | blob | history
src/arch/power/tlb.hh diff | blob | history
src/arch/sparc/tlb.hh diff | blob | history
src/arch/x86/faults.hh diff | blob | history
src/arch/x86/tlb.hh diff | blob | history
src/cpu/base_dyn_inst.hh diff | blob | history
src/cpu/checker/cpu.cc diff | blob | history
src/cpu/translation.hh diff | blob | history
src/sim/BaseTLB.py [deleted file] blob | history
src/sim/SConscript diff | blob | history
src/sim/tlb.cc [deleted file] blob | history
src/sim/tlb.hh [deleted file] blob | history