style: fix missing spaces in control statements
authorSteve Reinhardt <steve.reinhardt@amd.com>
Sun, 7 Feb 2016 01:21:19 +0000 (17:21 -0800)
committerSteve Reinhardt <steve.reinhardt@amd.com>
Sun, 7 Feb 2016 01:21:19 +0000 (17:21 -0800)
commit5592798865ece858bab2b444bc782d19121e2566
tree80803048c903c424ed9f1200b5dc1a29ed3ff6b8
parentdc8018a5c3482008232e6faaa2d96cf20aed7485
style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.
85 files changed:
src/arch/alpha/process.cc
src/arch/arm/insts/macromem.cc
src/arch/arm/insts/vfp.hh
src/arch/arm/kvm/arm_cpu.cc
src/arch/arm/linux/system.cc
src/arch/arm/tlb.cc
src/arch/generic/tlb.cc
src/arch/mips/isa.cc
src/arch/x86/bios/intelmp.cc
src/arch/x86/cpuid.cc
src/arch/x86/decoder.cc
src/arch/x86/insts/microldstop.cc
src/arch/x86/insts/microregop.cc
src/arch/x86/insts/static_inst.cc
src/arch/x86/insts/static_inst.hh
src/arch/x86/nativetrace.cc
src/arch/x86/pagetable_walker.cc
src/arch/x86/process.cc
src/arch/x86/types.hh
src/base/atomicio.hh
src/base/cp_annotate.cc
src/base/fenv.c
src/base/loader/elf_object.cc
src/base/statistics.cc
src/cpu/base.cc
src/cpu/kvm/perfevent.cc
src/cpu/kvm/x86_cpu.cc
src/cpu/minor/decode.cc
src/cpu/nativetrace.cc
src/cpu/nativetrace.hh
src/cpu/o3/inst_queue_impl.hh
src/cpu/o3/rename_impl.hh
src/cpu/pred/bpred_unit.cc
src/cpu/simple/atomic.cc
src/cpu/simple/base.cc
src/cpu/simple/timing.cc
src/dev/alpha/tsunami_cchip.cc
src/dev/arm/flash_device.cc
src/dev/arm/ufs_device.cc
src/dev/intel_8254_timer.cc
src/dev/mips/malta_cchip.cc
src/dev/virtio/base.cc
src/mem/bridge.cc
src/mem/cache/prefetch/stride.cc
src/mem/dram_ctrl.cc
src/mem/physical.cc
src/mem/port.cc
src/mem/ruby/filters/BulkBloomFilter.cc
src/mem/ruby/filters/H3BloomFilter.cc
src/mem/ruby/filters/MultiBitSelBloomFilter.cc
src/mem/ruby/filters/MultiGrainBloomFilter.cc
src/mem/ruby/filters/NonCountingBloomFilter.cc
src/mem/ruby/network/MessageBuffer.cc
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
src/mem/ruby/network/simple/PerfectSwitch.cc
src/mem/ruby/profiler/AccessTraceForAddress.cc
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/structures/AbstractReplacementPolicy.cc
src/mem/ruby/structures/BankedArray.cc
src/mem/ruby/structures/CacheMemory.cc
src/mem/ruby/structures/PseudoLRUPolicy.cc
src/mem/ruby/structures/RubyMemoryControl.cc
src/mem/ruby/structures/TBETable.hh
src/mem/ruby/system/GPUCoalescer.cc
src/mem/ruby/system/Sequencer.cc
src/mem/ruby/system/VIPERCoalescer.cc
src/mem/ruby/system/WeightedLRUPolicy.cc
src/mem/serial_link.cc
src/mem/stack_dist_calc.cc
src/python/swig/pyobject.cc
src/sim/backtrace_glibc.cc
src/sim/dvfs_handler.cc
src/sim/serialize.hh
src/sim/syscall_emul.hh
tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
tests/test-progs/gpu-hello/src/gpu-hello.cpp
tests/test-progs/mwait/mwait.c
util/statetrace/arch/amd64/tracechild.cc
util/statetrace/arch/arm/tracechild.cc
util/statetrace/arch/sparc/tracechild.cc
util/tlm/main.cc
util/tlm/sc_mm.cc
util/tlm/sc_port.cc
util/tlm/sc_target.cc