projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b1f400a) | patch
verilog_backend: dump attributes on CaseRule, as comments.
authorwhitequark <whitequark@whitequark.org>
Mon, 8 Jul 2019 12:48:50 +0000 (12:48 +0000)
committerwhitequark <whitequark@whitequark.org>
Mon, 8 Jul 2019 12:48:50 +0000 (12:48 +0000)
commit55c1f4027794a89971055b705254832b189a1c83
tree411b0132ec7cdb88b314b6eb79de2c1c5593dd96tree
parentb1f400aeb8de657d5fa28c153df14246378df2b1commit | diff
verilog_backend: dump attributes on CaseRule, as comments.

Attributes are not permitted in that position by Verilog grammar.
backends/verilog/verilog_backend.cc diff | blob | history