Merge pull request #60 from q3k/for-upstream/top-level-module-selection
authorenjoy-digital <florent@enjoy-digital.fr>
Mon, 19 Feb 2018 11:27:25 +0000 (12:27 +0100)
committerGitHub <noreply@github.com>
Mon, 19 Feb 2018 11:27:25 +0000 (12:27 +0100)
commit55fc9d2d6bdc343f569ded3ab3415f260f2a96ab
tree1e01de979846959db903e5fbae55da568c6daa4b
parent7b5bd4041a13720f4074bf284ef6735c76dacd4c
parentef511e7edcddf7b13c56a5e41c08042801bee9ff
Merge pull request #60 from q3k/for-upstream/top-level-module-selection

Top module selection (for Verilator and Diamond)
litex/build/sim/core/Makefile