Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
authorEddie Hung <eddie@fpgeh.com>
Fri, 16 Aug 2019 22:40:53 +0000 (15:40 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 16 Aug 2019 22:40:53 +0000 (15:40 -0700)
commit562c9e362487e0aa3a3d250a1a0a8cfcf10cafaa
treed79265bbbdef31af071ece9a5943fa7391a5ce77
parent958be89c47ae4f11b5de07bc026bc2202e2ebc97
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
techlibs/xilinx/cells_sim.v