i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
authorJordan Justen <jordan.l.justen@intel.com>
Tue, 9 Jul 2013 22:36:32 +0000 (15:36 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Sat, 16 Aug 2014 03:11:41 +0000 (20:11 -0700)
commit56cdb55e38ca352a0d521d7aa69b46ffbd855192
tree0faa1b033b16d702644e082a978e6ffa87314db2
parent3da13aef012a7edd6d2b07452865812f072d4b01
i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface

(bf25ee2 for gen6)

Previously we would always find the 2D sub-surface of interest,
and then program the surface to this location. Now we always
program the 3DSTATE_DEPTH_BUFFER at the start of the surface.
To select the lod/slice, we utilize the lod & minimum array
element fields.

We also must disable brw_workaround_depthstencil_alignment for
gen >= 6. Now the hardware will handle alignment when rendering
to additional slices/LODs.

v3:
 * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_misc_state.c
src/mesa/drivers/dri/i965/gen6_blorp.cpp
src/mesa/drivers/dri/i965/gen6_depth_state.c