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(parent: 9faa1d3) | patch
back.rtlil: emit dummy logic to work around Verilog deficiencies.
authorwhitequark <whitequark@whitequark.org>
Sun, 23 Dec 2018 10:14:05 +0000 (10:14 +0000)
committerwhitequark <whitequark@whitequark.org>
Sun, 23 Dec 2018 10:14:42 +0000 (10:14 +0000)
commit57027672632844176193ad75ceb8d5196d1b1aba
tree827c19b64c7da1a4a22cf2a922c6cdc683f773a1tree
parent9faa1d37425ddafb5b2e76d502d86e3bff9ae54ccommit | diff
back.rtlil: emit dummy logic to work around Verilog deficiencies.
nmigen/back/rtlil.py diff | blob | history