arch-riscv: fix GDB register cache
authorAlec Roelke <alec.roelke@gmail.com>
Tue, 6 Aug 2019 22:11:33 +0000 (18:11 -0400)
committerAlec Roelke <alec.roelke@gmail.com>
Fri, 23 Aug 2019 23:13:40 +0000 (23:13 +0000)
commit579c2cd54b1b29e8283f789a5bb221edb53e6f83
tree06fcc2a3cc7a786ffa62bed947e69a10da795a88
parent41f38a559b6b6ed50d821f16b742575d1487d1cf
arch-riscv: fix GDB register cache

Fixes the definition of the RISC-V GDB register cache.  The latest
version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8,
appears to only accept the 32 integer registers + the PC in the 'g'
packet.

This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*),
but works best with the Newlib toolchain (riscv64-unknown-elf-*).

Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20028
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/remote_gdb.cc
src/arch/riscv/remote_gdb.hh