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(parent: 10b4b36) | patch
X86: Read the LDT/GDT at CPL0 when executing an iret.
authorTim Harris <tharris@microsoft.com>
Mon, 7 Feb 2011 23:05:28 +0000 (15:05 -0800)
committerTim Harris <tharris@microsoft.com>
Mon, 7 Feb 2011 23:05:28 +0000 (15:05 -0800)
commit5810ab121c39f041aa6728696bc19e2e963eef90
treefe4d1c6ea7e109d84c5516b4fa59361c732f8016tree
parent10b4b364d9d42bcefda7ff18e1de9152dc6456d1commit | diff
X86: Read the LDT/GDT at CPL0 when executing an iret.

During iret access LDT/GDT at CPL0 rather than after transition to user mode
(if I'm reading the Intel IA-64 architecture spec correctly, the contents of
the descriptor table are read before the CPL is updated).
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py diff | blob | history