soc_core: adapt memory map for mainline Linux with mor1kx
authorFilip Kokosinski <fkokosinski@internships.antmicro.com>
Thu, 19 Sep 2019 10:23:05 +0000 (12:23 +0200)
committerMateusz Holenko <mholenko@antmicro.com>
Mon, 23 Sep 2019 13:34:52 +0000 (15:34 +0200)
commit5844376d53159dcbd0584c4489903d76b22fcd65
tree3f96c10578d3d6a87771df657b8f3388e8ad773d
parent201218b2c32555fc77da7b9009b1af96a602c082
soc_core: adapt memory map for mainline Linux with mor1kx

Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.
litex/soc/integration/soc_core.py
litex/soc/software/bios/boot.c