Add abc_arrival to SRL*
authorEddie Hung <eddie@fpgeh.com>
Wed, 21 Aug 2019 18:27:42 +0000 (11:27 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 21 Aug 2019 18:27:42 +0000 (11:27 -0700)
commit584c68069194f7c776755c108801a56898e19fff
tree434cfd3963190905579a7a17911476637e79d9af
parent8182cb9d91555d5be52abbfeeb5d22af05342d8a
Add abc_arrival to SRL*
techlibs/xilinx/cells_sim.v