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(parent: 32bd0f2) | patch
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
authorClifford Wolf <clifford@clifford.at>
Fri, 29 Mar 2019 15:32:44 +0000 (16:32 +0100)
committerClifford Wolf <clifford@clifford.at>
Fri, 29 Mar 2019 15:32:44 +0000 (16:32 +0100)
commit584d2030bf53c703febe8fda9cae73c72416c6cc
tree35cd5485c70c17e93426d54a104018bae90ed924tree
parent32bd0f22ec93202e67395901cdc64c20df7f0da7commit | diff
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906

Signed-off-by: Clifford Wolf <clifford@clifford.at>
frontends/verilog/Makefile.inc diff | blob | history