Add abc9_arrival times for RAM{32,64}M
authorEddie Hung <eddie@fpgeh.com>
Fri, 20 Dec 2019 22:06:59 +0000 (14:06 -0800)
committerEddie Hung <eddie@fpgeh.com>
Fri, 20 Dec 2019 22:06:59 +0000 (14:06 -0800)
commit5986a4df40a9c19171624c772b39e4c003e9c6ff
tree91512adc8a0abc04b289f59b80d33ba93e74842a
parent7928eb113c5a310924f4bb8ab26d0dafe902d6ec
Add abc9_arrival times for RAM{32,64}M
techlibs/xilinx/cells_sim.v