litedram: Remove old "VexRiscV" based initializations
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 5 Jun 2020 01:15:35 +0000 (11:15 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 5 Jun 2020 01:23:04 +0000 (11:23 +1000)
commit599fad117bef2805a08f7ee8b8fbd92cfc0ceb2c
tree7a3bf37e4afe3f7e927fbcc5a8dbb0b4d997161a
parenteaf6883e5720b185d369debf3ef1321ddc5b9b51
litedram: Remove old "VexRiscV" based initializations

Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
17 files changed:
Makefile
litedram/extras/VexRiscv.v [deleted file]
litedram/extras/fusesoc-add-files.py
litedram/extras/litedram-wrapper-l2.vhdl [new file with mode: 0644]
litedram/extras/wrapper-mw-init.vhdl [deleted file]
litedram/extras/wrapper-self-init.vhdl [deleted file]
litedram/gen-src/arty.yml
litedram/gen-src/generate.py
litedram/gen-src/nexys-video.yml
litedram/gen-src/sim.yml
litedram/generated/arty/init-cpu.txt [deleted file]
litedram/generated/arty/litedram_core.v
litedram/generated/nexys-video/init-cpu.txt [deleted file]
litedram/generated/nexys-video/litedram_core.v
litedram/generated/sim/init-cpu.txt [deleted file]
litedram/generated/sim/litedram_core.init
litedram/generated/sim/litedram_core.v