litex_sim: Rework Makefiles to put output files in gateware directory.
authorTim 'mithro' Ansell <me@mith.ro>
Sun, 12 Apr 2020 01:26:15 +0000 (18:26 -0700)
committerTim 'mithro' Ansell <me@mith.ro>
Sun, 12 Apr 2020 01:37:03 +0000 (18:37 -0700)
commit5a0bb6ee017f78a38a314747d55a95dbe10622c3
tree3d0d761d5febaedb7a7a6af018d60c8cd68c3156
parenta0658421ccdc63dff6182ff5cf8c66f25c5774d0
litex_sim: Rework Makefiles to put output files in gateware directory.
litex/build/sim/core/Makefile
litex/build/sim/core/modules/Makefile
litex/build/sim/core/modules/clocker/Makefile
litex/build/sim/core/modules/ethernet/Makefile
litex/build/sim/core/modules/jtagremote/Makefile
litex/build/sim/core/modules/rules.mak
litex/build/sim/core/modules/serial2console/Makefile
litex/build/sim/core/modules/serial2tcp/Makefile
litex/build/sim/core/modules/variables.mak [deleted file]
litex/build/sim/core/modules/xgmii_ethernet/Makefile
litex/build/sim/verilator.py