dev-arm: Make generic timer work with level-sensitive support
authorHsuan Hsu <hsuan.hsu@mediatek.com>
Wed, 27 May 2020 07:41:39 +0000 (15:41 +0800)
committerHsuan Hsu <kugwa2000@gmail.com>
Fri, 10 Jul 2020 18:03:15 +0000 (18:03 +0000)
commit5a55a242ab634c539af0ed4eb90f013b6d2b317d
treed8c55e6bf7995b917d8a9a557d1a6c7bb362636b
parent98ce167176838661833aa43fd8334ca1a0a0a23d
dev-arm: Make generic timer work with level-sensitive support

Support for level-sensitive PPIs and SPIs has been added to GICv2 now.
It is therefore the timer's responsibility to notify GICv2 to clear its
interrupt pending state. Without doing this, the guest will get stuck
in just a single round of the interrupt handler because GICv2 does not
clear the pending state, and eventually make the guest treat this
interrupt as problematic and then just disable it.

JIRA: https://gem5.atlassian.net/browse/GEM5-663

Change-Id: Ia8fd96bf00b28e91aa440274e6f8bb000446fbe3
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30916
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/dev/arm/generic_timer.cc