MEM: Introduce the master/slave port roles in the Python classes
authorAndreas Hansson <andreas.hansson@arm.com>
Mon, 13 Feb 2012 11:43:09 +0000 (06:43 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Mon, 13 Feb 2012 11:43:09 +0000 (06:43 -0500)
commit5a9a743cfc4517f93e5c94533efa767b92272c59
treef3dbc078a51e5759b26b1a5f16263ddb1cf55a7b
parent8cb4a2208d568eb86ad3f6c6bb250bcbe2952302
MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
65 files changed:
configs/common/CacheConfig.py
configs/common/FSConfig.py
configs/example/fs.py
configs/example/ruby_fs.py
configs/example/se.py
configs/ruby/Ruby.py
src/arch/arm/ArmTLB.py
src/arch/x86/X86LocalApic.py
src/arch/x86/X86TLB.py
src/arch/x86/interrupts.hh
src/cpu/BaseCPU.py
src/cpu/simple/AtomicSimpleCPU.py
src/cpu/testers/directedtest/RubyDirectedTester.py
src/cpu/testers/memtest/MemTest.py
src/cpu/testers/networktest/NetworkTest.py
src/cpu/testers/rubytest/RubyTester.py
src/dev/Device.py
src/dev/Ethernet.py
src/dev/Pci.py
src/dev/alpha/Tsunami.py
src/dev/arm/RealView.py
src/dev/x86/I82094AA.py
src/dev/x86/Pc.py
src/dev/x86/SouthBridge.py
src/dev/x86/i82094aa.hh
src/dev/x86/intdev.hh
src/mem/Bridge.py
src/mem/Bus.py
src/mem/PhysicalMemory.py
src/mem/cache/BaseCache.py
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/Sequencer.py
src/python/m5/SimObject.py
src/python/m5/params.py
src/sim/System.py
tests/configs/inorder-timing.py
tests/configs/memtest-ruby.py
tests/configs/memtest.py
tests/configs/o3-timing-mp-ruby.py
tests/configs/o3-timing-mp.py
tests/configs/o3-timing-ruby.py
tests/configs/o3-timing.py
tests/configs/pc-o3-timing.py
tests/configs/pc-simple-atomic.py
tests/configs/pc-simple-timing.py
tests/configs/realview-o3-dual.py
tests/configs/realview-o3.py
tests/configs/realview-simple-atomic-dual.py
tests/configs/realview-simple-atomic.py
tests/configs/realview-simple-timing-dual.py
tests/configs/realview-simple-timing.py
tests/configs/rubytest-ruby.py
tests/configs/simple-atomic-mp-ruby.py
tests/configs/simple-atomic-mp.py
tests/configs/simple-atomic.py
tests/configs/simple-timing-mp.py
tests/configs/simple-timing.py
tests/configs/tsunami-inorder.py
tests/configs/tsunami-o3-dual.py
tests/configs/tsunami-o3.py
tests/configs/tsunami-simple-atomic-dual.py
tests/configs/tsunami-simple-atomic.py
tests/configs/tsunami-simple-timing-dual.py
tests/configs/tsunami-simple-timing.py
tests/configs/twosys-tsunami-simple-atomic.py