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(parent: 862e784) | patch
soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 16 Jan 2020 18:45:41 +0000 (19:45 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 16 Jan 2020 18:45:41 +0000 (19:45 +0100)
commit5aa516cb8d8ee32424b593061cc723bc3d61c70b
tree5ca93b96c49c999ce99bc2ec194898c517a462c2tree
parent862e784eaefa41a05d92caa132d73b25205ad74ccommit | diff
soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.

When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
litex/soc/cores/uart.py diff | blob | history