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(parent: 4e977bf) | patch
Add PLL for ECP5 device
authorMichael Neuling <mikey@neuling.org>
Tue, 7 Jul 2020 11:15:34 +0000 (21:15 +1000)
committerMichael Neuling <mikey@neuling.org>
Tue, 7 Jul 2020 12:28:58 +0000 (22:28 +1000)
commit5aaa63ee3ba2a12eb7078e6fc3fe47a016a6c11f
tree2a039e90439d21d592a18dff1bf61739a0a4e735tree
parent4e977bf8a94ab9697a997ab36d405394051a3f04commit | diff
Add PLL for ECP5 device

Means we can synthesize at 40Mhz (where we currently make timing) and
our UART still works at 115200 baud.

Tested working hello world unmodified with ECP5 eval board. Orange
Crab is updated but is untested.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Makefile diff | blob | history
fpga/clk_gen_ecp5.vhd [new file with mode: 0644] blob