arch-arm: SVE instructions do not use AHP format
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 22 Apr 2020 16:24:26 +0000 (17:24 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 27 Apr 2020 13:10:45 +0000 (13:10 +0000)
commit5b23b6ea018575428f4119e3042ec6d8fb03f120
tree92f4bb439677c2aab0959a8119d30e0e7fc5788c
parentb089163b72812366def0c07d9d0ea27bb580b20e
arch-arm: SVE instructions do not use AHP format

SVE half-precision floating-point instructions support only IEEE
754-2008 half-precision format and ignore the value of the FPCR.AHP bit,
behaving as if it has an Effective value of 0.

This patch is addressing this by masking the FPSCR.AHB bit before
passing it to fplib.

Change-Id: I1432fc3f7fefb81445fe042ae7d681f5cec40e64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28108
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/isa/insts/sve.isa
src/arch/arm/miscregs.hh