Accept real-valued delay values
authorClifford Wolf <clifford@clifford.at>
Sat, 18 Nov 2017 09:01:30 +0000 (10:01 +0100)
committerClifford Wolf <clifford@clifford.at>
Sat, 18 Nov 2017 09:01:30 +0000 (10:01 +0100)
commit5b6e52118c09bb5967efc2bc2ebe53b9608bad89
tree53c2f27ccaa5cfaeb6f07bf61a1a49ff22e58f3b
parenta4195e83c74bb4d69be181077923d2cb94bfcfc6
Accept real-valued delay values
frontends/verilog/verilog_parser.y