intel_alm: direct LUTRAM cell instantiation
authorDan Ravensloft <dan.ravensloft@gmail.com>
Thu, 16 Apr 2020 11:24:04 +0000 (12:24 +0100)
committerMarcelina Koƛcielnicka <mwk@0x04.net>
Thu, 7 May 2020 19:03:13 +0000 (21:03 +0200)
commit5b779f7f4ef0bf2c4ad3a412da24fad30b078626
treecb0fcd56575efe8a846fbd6a2888aee80998f644
parent06104249406972de01d0360df63a32cafcdf2ec5
intel_alm: direct LUTRAM cell instantiation

By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
techlibs/intel_alm/Makefile.inc
techlibs/intel_alm/common/bram_m10k_map.v
techlibs/intel_alm/common/lutram_mlab.txt
techlibs/intel_alm/common/lutram_mlab_map.v [deleted file]
techlibs/intel_alm/common/megafunction_bb.v
techlibs/intel_alm/common/mem_sim.v [new file with mode: 0644]
techlibs/intel_alm/common/quartus_rename.v
techlibs/intel_alm/synth_intel_alm.cc
tests/arch/intel_alm/lutram.ys [new file with mode: 0644]