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(parent: e801dc0) | patch
add fractional division options to clk0 config on PLL
authorbunnie <bunnie@kosagi.com>
Tue, 10 Mar 2020 10:48:30 +0000 (18:48 +0800)
committerbunnie <bunnie@kosagi.com>
Tue, 10 Mar 2020 10:48:30 +0000 (18:48 +0800)
commit5b92bf2d575416739995b9f5905654a72fdcacb3
treec53c2c9efafd1b8c8a37a5cc8e76604aa1eb059ftree
parente801dc0261d7101b148135933f441ed82ca61da8commit | diff
add fractional division options to clk0 config on PLL

S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.

This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
litex/soc/cores/clock.py diff | blob | history