Merge pull request #2045 from YosysHQ/eddie/fix2042
authorEddie Hung <eddie@fpgeh.com>
Thu, 14 May 2020 16:45:54 +0000 (09:45 -0700)
committerGitHub <noreply@github.com>
Thu, 14 May 2020 16:45:54 +0000 (09:45 -0700)
commit5bcde7ccc331e575682823222c97cc414bb3d808
tree07405fdd0d0652ad75bb881ef67fa66a5e3315a3
parentf02e20907e5d0f343c83ed1a762a39299105167e
parent56a5b1d2daf1b244990d81f32183034071ebd185
Merge pull request #2045 from YosysHQ/eddie/fix2042

verilog: error if no direction given for task arguments, default to input in SV mode