test: generate examples to verilog as part of unit tests.
authorwhitequark <whitequark@whitequark.org>
Mon, 8 Jul 2019 10:12:15 +0000 (10:12 +0000)
committerwhitequark <whitequark@whitequark.org>
Mon, 8 Jul 2019 10:12:26 +0000 (10:12 +0000)
commit5c63177fc2fb7b05bad063c02a6402aa5da0b73a
treec0c6c98a53f2348a80d1015b9dff5ebebbdb98b8
parentc14d074fcc70ed3bc328fbfb930416b41f055a2c
test: generate examples to verilog as part of unit tests.

This is to make sure 806a62c2 doesn't happen again.
examples/basic/arst.py
nmigen/test/test_examples.py [new file with mode: 0644]