rs6000: Make the ctr* patterns allow ints in vector regs (PR71763)

rs6000: Make the ctr* patterns allow ints in vector regs (PR71763)

Similar to PR70098, which is about integers in floating point registers,
we can have the completely analogous problem with vector registers as well
now that we allow integers in vector registers.  So, this patch solves it
in the same way.  This only works for targets with direct move.

To recap: register allocation can decide to put an integer mode value in
a floating point or vector register.  If that register is used in a bd*z
instruction, which is a jump instruction, reload can not do an output
reload on it (it does not do output reloads on any jump insns), so the
float or vector register will remain, and we have to allow it here or
recog will ICE.  Later on we will split this to valid instructions,
including a move from that fp/vec register to an int register; it is this
move that will still fail (PR70098) if we do not have direct move enabled.

	PR target/70098
	PR target/71763
	* config/rs6000/rs6000.md (*ctr<mode>_internal1, *ctr<mode>_internal2,
	*ctr<mode>_internal5, *ctr<mode>_internal6): Add *wi to the output
	constraint.

gcc/testsuite/
	PR target/70098
	PR target/71763
	* gcc.target/powerpc/pr71763.c: New file.

From-SVN: r238076