git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Wed, 26 Sep 2018 08:03:08 +0000 (09:03 +0100)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Wed, 26 Sep 2018 08:03:08 +0000 (09:03 +0100)
commit	5de2a58256f8d26f27b551cf9664237949f40a31
tree	2bb5e9156da45f8d175b81c4c6bcb3cb6e7fac26	tree
parent	8b926a3ba55b2e4adb8fcbac386809b86efc8ea1	commit \| diff

check if register redirection is active, and if vectorisation enabled

check each register (if used) - this is what the #define USING_RD etc.
macros are for, to disable checks that are not needed

riscv/insn_template_sv.cc		diff \| blob \| history
riscv/sv.cc		diff \| blob \| history
riscv/sv.h		diff \| blob \| history

Simple-V augmented version of spike

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