arch-riscv: enable rudimentary fs simulation
authorRobert <robert.scheffel1@tu-dresden.de>
Tue, 13 Mar 2018 13:29:00 +0000 (14:29 +0100)
committerRobert Scheffel <robert.scheffel1@tu-dresden.de>
Mon, 9 Jul 2018 11:17:11 +0000 (11:17 +0000)
commit5de8ca95506a5f15bfbfdd2ca9babd282a882d1f
tree1bc429aa1896dea5167e37000428d157b1a0b710
parent98cbcbb54f56475759fae747b60e47568617640f
arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
12 files changed:
src/arch/riscv/RiscvSystem.py
src/arch/riscv/SConscript
src/arch/riscv/bare_metal/system.cc [new file with mode: 0644]
src/arch/riscv/bare_metal/system.hh [new file with mode: 0644]
src/arch/riscv/faults.cc
src/arch/riscv/faults.hh
src/arch/riscv/interrupts.hh
src/arch/riscv/system.cc
src/arch/riscv/system.hh
src/arch/riscv/tlb.cc
src/arch/riscv/utility.cc [new file with mode: 0644]
src/arch/riscv/utility.hh