hierarchy: Resolve SV wildcard port connections
authorDavid Shah <dave@ds0.me>
Fri, 22 Nov 2019 09:04:54 +0000 (09:04 +0000)
committerDavid Shah <dave@ds0.me>
Sun, 2 Feb 2020 16:12:33 +0000 (16:12 +0000)
commit5df591c02309c086229029808c21ab8721278888
tree0405b135a313ebb1da7a6d1597f670b3f2582e26
parent50f86c11b2bb9e561f5a0cf10e053b1aa4918abd
hierarchy: Resolve SV wildcard port connections

Signed-off-by: David Shah <dave@ds0.me>
frontends/verilog/verilog_parser.y
passes/hierarchy/hierarchy.cc