arch-riscv: Fix disassembling of jalr
authorIan Jiang <ianjiang.ict@gmail.com>
Fri, 21 Aug 2020 10:46:04 +0000 (18:46 +0800)
committerIan Jiang <ianjiang.ict@gmail.com>
Fri, 28 Aug 2020 00:22:00 +0000 (00:22 +0000)
commit5e1bc74efe5a536d6d0dcd3676786c72adbf1087
tree49f37dfcd4ba4b6f1380e640dc632108eada2447
parent6ff5fc5c1c5991265d26863bd3a9d268341a70b1
arch-riscv: Fix disassembling of jalr

The 'jalr' instruction of 'format Jump' should have an immediate as
offset, and the Rd register could not be always omitted. This patch
fixes the problem.

Example output:
  jalr ra, -168(ra)
  jalr zero, 0(ra)
  jalr ra, 0(a5)

Note that this does not apply to the other two instructions of the
same format: 'c.jr' and 'c.jalr'.

Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/isa/formats/standard.isa