arch, cpu: Architectural Register structural indexing
authorNathanael Premillieu <nathanael.premillieu@arm.com>
Wed, 5 Apr 2017 17:46:06 +0000 (12:46 -0500)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Wed, 5 Jul 2017 14:43:49 +0000 (14:43 +0000)
commit5e8287d2e2eaf058495442ea9e32fafc343a0b53
tree7d0891b8984926f8e404d6ca8247f45695f9fc9b
parent864f87f9c56a66dceeca0f4e9470fbaa3001b627
arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
70 files changed:
src/arch/alpha/isa/branch.isa
src/arch/alpha/isa/fp.isa
src/arch/alpha/isa/main.isa
src/arch/alpha/registers.hh
src/arch/arm/insts/branch64.cc
src/arch/arm/insts/data64.cc
src/arch/arm/insts/macromem.cc
src/arch/arm/insts/mem.cc
src/arch/arm/insts/mem.hh
src/arch/arm/insts/mem64.cc
src/arch/arm/insts/misc.cc
src/arch/arm/insts/misc64.cc
src/arch/arm/insts/static_inst.cc
src/arch/arm/insts/static_inst.hh
src/arch/arm/insts/vfp.cc
src/arch/arm/registers.hh
src/arch/generic/types.hh
src/arch/isa_parser.py
src/arch/mips/isa/base.isa
src/arch/mips/isa/decoder.isa
src/arch/mips/isa/formats/int.isa
src/arch/mips/isa/formats/mt.isa
src/arch/mips/mt.hh
src/arch/mips/registers.hh
src/arch/null/registers.hh
src/arch/power/insts/branch.cc
src/arch/power/insts/static_inst.cc
src/arch/power/insts/static_inst.hh
src/arch/power/registers.hh
src/arch/riscv/isa/base.isa
src/arch/riscv/isa/formats/type.isa
src/arch/riscv/registers.hh
src/arch/sparc/isa/base.isa
src/arch/sparc/isa/formats/integerop.isa
src/arch/sparc/isa/formats/mem/util.isa
src/arch/sparc/isa/formats/priv.isa
src/arch/sparc/registers.hh
src/arch/x86/insts/microfpop.hh
src/arch/x86/insts/microldstop.hh
src/arch/x86/insts/micromediaop.hh
src/arch/x86/insts/microregop.hh
src/arch/x86/insts/static_inst.cc
src/arch/x86/insts/static_inst.hh
src/arch/x86/isa/microops/limmop.isa
src/arch/x86/isa/specialize.isa
src/arch/x86/registers.hh
src/cpu/base_dyn_inst.hh
src/cpu/checker/cpu.hh
src/cpu/checker/cpu_impl.hh
src/cpu/exec_context.hh
src/cpu/minor/dyn_inst.cc
src/cpu/minor/dyn_inst.hh
src/cpu/minor/exec_context.hh
src/cpu/minor/scoreboard.cc
src/cpu/minor/scoreboard.hh
src/cpu/o3/cpu.cc
src/cpu/o3/dyn_inst.hh
src/cpu/o3/dyn_inst_impl.hh
src/cpu/o3/probe/elastic_trace.cc
src/cpu/o3/rename.hh
src/cpu/o3/rename_impl.hh
src/cpu/o3/rename_map.cc
src/cpu/o3/rename_map.hh
src/cpu/o3/rob.hh
src/cpu/reg_class.cc
src/cpu/reg_class.hh
src/cpu/simple/exec_context.hh
src/cpu/static_inst.hh
src/cpu/thread_context.hh
src/cpu/timing_expr.cc