hdl.mem: use more informative signal naming for ports.
authorwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 23:55:02 +0000 (23:55 +0000)
committerwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 23:55:02 +0000 (23:55 +0000)
commit5ea35d005486879ea12566bc75d207b37f6088e0
tree938a5fd311e44c58de670ad3f7abe3467a72635c
parent2fc2461c0ad17a9cd085ab2398813a6cf4e2214e
hdl.mem: use more informative signal naming for ports.
nmigen/hdl/mem.py