RISC-V: Add support for the Zvksed ISA extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Fri, 30 Jun 2023 20:44:01 +0000 (22:44 +0200)
committerJeff Law <jlaw@ventanamicro>
Sat, 1 Jul 2023 13:28:40 +0000 (07:28 -0600)
commit5ec6edd0a215651c4d20984b48095941167e2c0a
tree18c785a7b40b519e207980741229aec5c67975b1
parent62edb233ef5fff5356c46570b3ba19dcbe6ceb35
RISC-V: Add support for the Zvksed ISA extension

Zvksed is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]

bfd/ChangeLog:

* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvksed.
(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

* testsuite/gas/riscv/zvksed.d: New test.
* testsuite/gas/riscv/zvksed.s: New test.

include/ChangeLog:

* opcode/riscv-opc.h (MATCH_VSM4K_VI): New.
(MASK_VSM4K_VI): New.
(MATCH_VSM4R_VS): New.
(MASK_VSM4R_VS): New.
(MATCH_VSM4R_VV): New.
(MASK_VSM4R_VV): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvksed.

opcodes/ChangeLog:

* riscv-opc.c: Add Zvksed instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/elfxx-riscv.c
gas/testsuite/gas/riscv/zvksed.d [new file with mode: 0644]
gas/testsuite/gas/riscv/zvksed.s [new file with mode: 0644]
include/opcode/riscv-opc.h
include/opcode/riscv.h
opcodes/riscv-opc.c