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(parent: c34d1cc) | patch
x86: have insns acting on segment selector values allow for consistent operands
authorJan Beulich <jbeulich@suse.com>
Fri, 24 Feb 2023 12:57:31 +0000 (13:57 +0100)
committerJan Beulich <jbeulich@suse.com>
Fri, 24 Feb 2023 12:57:31 +0000 (13:57 +0100)
commit5eeeafe0a6884eaf1c5a21160e78e53842fa7cba
treeccae730941360b00b9870cf3f271701d2e368527tree
parentc34d1cc9200ae24dc7572aaf77d80276c0490e9bcommit | diff
x86: have insns acting on segment selector values allow for consistent operands

While MOV to/from segment register as well as selector storing insns
already permit 32- and 64-bit GPR operands, selector loading insns and
ARPL do not. Split templates accordingly.
gas/config/tc-i386-intel.c diff | blob | history
gas/testsuite/gas/i386/i386-intel.d diff | blob | history
gas/testsuite/gas/i386/i386.d diff | blob | history
gas/testsuite/gas/i386/i386.s diff | blob | history
gas/testsuite/gas/i386/x86_64-intel.d diff | blob | history
gas/testsuite/gas/i386/x86_64.d diff | blob | history
gas/testsuite/gas/i386/x86_64.s diff | blob | history
opcodes/i386-opc.tbl diff | blob | history
opcodes/i386-tbl.h diff | blob | history