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(parent: 716e447) | patch
inorder/dtb: make sure DTB translate correct address
authorKorey Sewell <ksewell@umich.edu>
Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)
committerKorey Sewell <ksewell@umich.edu>
Mon, 20 Jun 2011 01:43:41 +0000 (21:43 -0400)
commit5ef0b7a9db3c6ec4ca191c2e9381719e1e694873
tree718fdaf81b288b91bbac7eb2a8bae285d2dc39actree
parent716e447da8424386f2c3448c17891927aeb49f67commit | diff
inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
src/arch/alpha/tlb.cc diff | blob | history
src/cpu/inorder/resources/cache_unit.cc diff | blob | history