soc/cpu: add memory_buses to cpus and use them in add_sdram.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 27 Apr 2020 21:51:17 +0000 (23:51 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 27 Apr 2020 21:53:52 +0000 (23:53 +0200)
commit5ef869b9ebdcbfbe037e1fee6a06866a2837a168
tree56a779a23fa47cd4c1f07e85eefe279ab6d4a1f4
parent467fee3e236e21adb0debe6bd4be07bda4558b4d
soc/cpu: add memory_buses to cpus and use them in add_sdram.

This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
litex/soc/cores/cpu/__init__.py
litex/soc/cores/cpu/blackparrot/core.py
litex/soc/cores/cpu/lm32/core.py
litex/soc/cores/cpu/microwatt/core.py
litex/soc/cores/cpu/minerva/core.py
litex/soc/cores/cpu/mor1kx/core.py
litex/soc/cores/cpu/picorv32/core.py
litex/soc/cores/cpu/rocket/core.py
litex/soc/cores/cpu/serv/core.py
litex/soc/cores/cpu/vexriscv/core.py
litex/soc/integration/soc.py