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(parent: 63fa5fd) | patch
i965: Allocate destination registers for GLSL TEX instructions contiguously.
authorEric Anholt <eric@anholt.net>
Wed, 12 Aug 2009 20:17:15 +0000 (13:17 -0700)
committerEric Anholt <eric@anholt.net>
Wed, 12 Aug 2009 20:18:47 +0000 (13:18 -0700)
commit5faa0dc591527683e32306456cbfe6d93afa04da
treee76e9df73d6f68255446b2c9f60d074d88fe1c02tree
parent63fa5fd319c0d0114085f47f028a36f63c1f7295commit | diff
i965: Allocate destination registers for GLSL TEX instructions contiguously.

This matches brw_wm_pass*.c behavior, and fixes the norsetto shadow demo.

Bug #19489
src/mesa/drivers/dri/i965/brw_wm_glsl.c diff | blob | history