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(parent: 8aa3fb3) | patch
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 1 May 2015 14:11:15 +0000 (16:11 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 1 May 2015 14:11:15 +0000 (16:11 +0200)
commit603b4cdc8cb3cbbfe1abc2e24a0d4e6e58c421f8
tree13452b4448307a41575de8e037acff54f58301d2tree
parent8aa3fb3eb707e6a3c72979d870f393398f022479commit | diff
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)

- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
13 files changed:
misoclib/com/liteusb/common.py diff | blob | history
misoclib/com/liteusb/core/__init__.py diff | blob | history
misoclib/com/liteusb/core/crossbar.py diff | blob | history
misoclib/com/liteusb/core/packet.py diff | blob | history
misoclib/com/liteusb/frontend/dma.py diff | blob | history
misoclib/com/liteusb/frontend/uart.py diff | blob | history
misoclib/com/liteusb/phy/ft2232h.py [deleted file] blob | history
misoclib/com/liteusb/phy/ft245.py [new file with mode: 0644] blob
misoclib/com/liteusb/test/Makefile diff | blob | history
misoclib/com/liteusb/test/ft2232h_async_tb.py [deleted file] blob | history
misoclib/com/liteusb/test/ft2232h_sync_tb.py [deleted file] blob | history
misoclib/com/liteusb/test/ft245_async_tb.py [new file with mode: 0644] blob
misoclib/com/liteusb/test/ft245_sync_tb.py [new file with mode: 0644] blob