soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq).
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 20 Mar 2020 18:49:42 +0000 (19:49 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 20 Mar 2020 18:49:42 +0000 (19:49 +0100)
commit61c9e54a9029bd9181de6738ade93ad44e4a18fc
tree16343f523bc52a3d2325c32ea14ebf5e0d4ff472
parentdd7718b4fe1f5dc797f210c4445e1ea1d5845095
soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq).
litex/soc/cores/spi.py