fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 24 Sep 2021 04:24:37 +0000 (14:24 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Sat, 25 Sep 2021 08:18:32 +0000 (18:18 +1000)
commit621a0f6b285f377fc5e8827918c8200d5ae80729
tree1772ccf75581c597ea22d730fb6f29d5b724994c
parent4b1a413a2fe7ac6657295a4a7a7d10b4596d61b4
fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz

50Mhz clkin, 100Mhz sys_clk, as needed for Wukon v2

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
fpga/clk_gen_plle2.vhd