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(parent: 6e3b25e) | patch
fhdl/verilog: do not attempt to initialize instance and mem output signals
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 2 Apr 2012 10:59:42 +0000 (12:59 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 2 Apr 2012 10:59:42 +0000 (12:59 +0200)
commit623e8e436a4bf044a3cc0ac35e338650b6a90d3a
tree56e37ca1e6ad785c7c28d87760fb2a7db17e52e5tree
parent6e3b25ebb6512a9f03ad3bab1d3df0eabe0b132acommit | diff
fhdl/verilog: do not attempt to initialize instance and mem output signals
migen/fhdl/verilog.py diff | blob | history