projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 48655df) | patch
verilog_backend: dump attributes on SwitchRule.
authorwhitequark <whitequark@whitequark.org>
Mon, 8 Jul 2019 15:11:29 +0000 (15:11 +0000)
committerwhitequark <whitequark@whitequark.org>
Mon, 8 Jul 2019 15:11:29 +0000 (15:11 +0000)
commit628437b01cd37b95c020b2f4c4e2f2d8f0e9bf8b
treea7ee0c5daa8701c505665dbf936aa0c957b83fdbtree
parent48655dfb8b4dda7607ed7a790eb5f6bce5c27d38commit | diff
verilog_backend: dump attributes on SwitchRule.

This appears to be an omission.
backends/verilog/verilog_backend.cc diff | blob | history