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(parent: 268c9d8) | patch
arch-riscv: added support for pseudo instructions.
authorNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Tue, 18 Feb 2020 07:54:41 +0000 (08:54 +0100)
committerNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Thu, 26 Mar 2020 08:28:43 +0000 (08:28 +0000)
commit6362e8b2d2f1bfd3f6686fda8c43469b65b768c9
tree7e4fc5d31e3fabd9cfb79e5aee831ee6d9fefd82tree
parent268c9d836fb17cb35d4bc06f08659950fad33b0fcommit | diff
arch-riscv: added support for pseudo instructions.

Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25645
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
src/arch/riscv/insts/pseudo.hh [new file with mode: 0644] blob
src/arch/riscv/isa/bitfields.isa diff | blob | history
src/arch/riscv/isa/decoder.isa diff | blob | history
src/arch/riscv/isa/formats/formats.isa diff | blob | history
src/arch/riscv/isa/formats/m5ops.isa [new file with mode: 0644] blob
src/arch/riscv/isa/includes.isa diff | blob | history
src/arch/riscv/isa/operands.isa diff | blob | history
src/arch/riscv/utility.hh diff | blob | history