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(parent: f3eaa0f) | patch
First draft of Verilog parser support for specify blocks and parameters.
authorUdi Finkelstein <github@udifink.com>
Sun, 4 Mar 2018 21:35:08 +0000 (23:35 +0200)
committerClifford Wolf <clifford@clifford.at>
Tue, 27 Mar 2018 12:34:00 +0000 (14:34 +0200)
commit6378e2cd46711fed551ecf3201cee1f174d7053d
tree2560746b61bd2da76e8add38ca57adc30d086a09tree
parentf3eaa0ffa54ddaea4bf4e04acc1b2e019e22484acommit | diff
First draft of Verilog parser support for specify blocks and parameters.
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
frontends/verilog/verilog_lexer.l diff | blob | history
frontends/verilog/verilog_parser.y diff | blob | history
tests/simple/specify.v [new file with mode: 0644] blob