arch-riscv: Restructure ISA description
authorAlec Roelke <ar4jc@virginia.edu>
Thu, 15 Jun 2017 19:33:25 +0000 (15:33 -0400)
committerAlec Roelke <ar4jc@virginia.edu>
Tue, 11 Jul 2017 03:37:04 +0000 (03:37 +0000)
commit63d4005a29dea37e0219444a3de2cdb25289fdfb
tree88bf3070e642da6594cb51b9dfc5b2cf63b93bdb
parent91f965dd5708eb365f1b28d30f2c3f012519b1c2
arch-riscv: Restructure ISA description

This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.

[Fix class UImmOp to have an "imm" member rather than "uimm".]
[Update disassembly generation for new RegId class.]

Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Reviewed-on: https://gem5-review.googlesource.com/3800
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
15 files changed:
src/arch/riscv/isa.cc
src/arch/riscv/isa.hh
src/arch/riscv/isa/base.isa
src/arch/riscv/isa/bitfields.isa
src/arch/riscv/isa/decoder.isa
src/arch/riscv/isa/formats/amo.isa
src/arch/riscv/isa/formats/basic.isa
src/arch/riscv/isa/formats/formats.isa
src/arch/riscv/isa/formats/fp.isa
src/arch/riscv/isa/formats/mem.isa
src/arch/riscv/isa/formats/standard.isa [new file with mode: 0644]
src/arch/riscv/isa/formats/type.isa [deleted file]
src/arch/riscv/isa/includes.isa
src/arch/riscv/registers.hh
src/arch/riscv/utility.hh