soc/cores/cpu/vexriscv: move verilog variant selection to add_sources
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 9 Jan 2019 07:32:17 +0000 (08:32 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 9 Jan 2019 08:19:40 +0000 (09:19 +0100)
commit648015d78e487d9deaf9627d4aa2a6838669ee48
treead004a95e31ea43f6664f5bcefe75e53124400a8
parent2b5a6f1058fb7d38573b48e3a65572604dacf72a
soc/cores/cpu/vexriscv: move verilog variant selection to add_sources
litex/soc/cores/cpu/vexriscv/core.py